Integrated circuit (IC) devices include “mobile chips,” e.g., an IC device that is designed as a processing component, such as a central processing unit (CPU) for mobile or cellular communication or computing systems. Mobile chips and other IC devices may use active power management schemes to control, regulate and optimize power related characteristics of the devices.
Typical IC devices comprise a semiconductor die. An array of active device and addressable memory cell components (e.g., transistors) are disposed therein. The active and addressable components are operably configured within the array with an interconnective network conductive traces and vias. Conductive pads and leads allow signal inputs and outputs from the IC.
In general, sub-microscopic technology development diminishes the physical dimensions of IC devices even as the switching and logic frequencies and power consumption thereof rise. Smaller dimensions and faster logic and switching are particularly valuable in mobile chips, which comprise components in telephones, pad computers, personal digital assistants (PDA) and the like.
However, greater switching frequencies and power consumption may degrade reliability and/or performance in IC devices with such small, sub-microscopic dimensions. The inductance of conductive leads, for instance, may suffice to develop related di/dt voltage drops. These voltage drops may inject voltage related noise, which reduces noise margins and switching speeds.
Noise that is injected by di/dt voltage drops (hereinafter, “di/dt noise”) is voltage related noise, which may reach significant levels in relation to the core supply voltage (Vdd) of a multi-core CPU. FIG. 1 graphs an example di/dt noise profile 10. Noise profile 10 represents a pair of corresponding current (Idyn) and voltage (Vdd_cpu) noise waveforms that may characterize Vdd for an example 4-core CPU, which develops di/dt noise levels of as high as 20 percent of Vdd or more.
Significant noise signatures may constrain or limit the effective upper operating frequency that a CPU may achieve or sustain. This frequency constraint relates to maintaining sufficient timing margins to clock accurately even the CPU's fastest running logic and switching operations without error or failure. In some CPUs, dynamic voltage and frequency scaling (DVFS) may be used to help maintain sufficient timing margins, reactively in relation to di/dt noise on Vdd.
DVFS tables for the CPU domain are currently defined in software. For example, DVFS tables may group data tabulated therewith, e.g., using a per bin basis in which the data are at least partially quantized on the basis of the voltage levels they represent. The DVFS tables specify the Vdd voltage levels that are needed by all of the CPU components, which are tabulated in each of the bins, to run at any of a range of given frequencies.
This approach essentially involves adding an extra voltage margin for all parts in each of the bins to compensate for the slowest part in the bin. However, this extra voltage margin demands higher power, which raises temperatures and represents diminished efficiency.
Approaches described in this section could, but have not necessarily been conceived or pursued previously. Unless otherwise indicated, neither approaches described in this section, nor issues identified in relation thereto, are to be assumed as recognized in any prior art merely by inclusion therein.